1. Field of the Invention
The present invention relates to a high level synthesizing technique for automatically generating a register transfer level (abbreviated as “RTL”) description and, more particularly, to a design method of a logic circuit for converting an operation description into an RTL description.
2. Description of the Related Art
In a logic circuit design of the prior art, a table showing the correspondence between an intermediate signal in an operation description and an operation unit for a logic circuit has been developed.
However, in a higher level synthesized RTL description, data has been stored in a storage element for each execution step, and then, one operation unit has repeated the operations. Therefore, a table has not been provided which shows the correspondence therebetween, and further, no table has been provided showing the correspondence per each execution step. In the case where there is a failure in a simulation result of a logic circuit of the RTL description, a designer has analyzed the simulation result by using only the RTL description. Since the RTL description has been varied at an operating location according to an operating time or condition, such an analysis has taken a great deal of time.